1. Field of the Invention
The present invention relates to semiconductor layouts, and in particular to a layout for detecting overlap between active areas and deep trench capacitors in semiconductor memory cells.
2. Description of the Related Art
A semiconductor circuit usually comprises numerous features at a micron scale. These features are defined by photolithography and fabricated by multiple etching, oxidation, silicon oxide and metal deposition.
Because features on a semiconductor chip are defined by photolithography, the yield rate of semiconductor fabrication depends on alignment accuracy and the control of critical dimension effect. Thus, it is important for integrated semiconductor circuits to detect misalignment from overlap during fabrication.
Semiconductor memories such as dynamic random access memories (DRAM) typically include memory cells with storage nodes. Generally these storage nodes are formed within deep trenches etched into substrates of the semiconductor memory chip. The storage nodes are accessed using an access transistor which allows charges to be stored in the storage node or retrieves charges from the storage depending on whether the desired action is a read or write function.
The inherent leakage current inside the DRAM memory cells decreases charges in the capacitor with time. The capacitor has to be refreshed before the voltage falls below the threshold.
Referring to FIG. 1, a layout is shown for conventional deep trench capacitors. Deep trench capacitors 10 are disposed under passing word lines 12. Access transistors 14 are electrically coupled to storage nodes 16 of trench capacitors 10 through diffusion regions 18 which may be either a source or a drain of access transistors 14. Diffusion regions 20 are also included, electrically connected to contacts 22. Contacts 22 connect to bit lines (not shown) to read from and write to storage nodes 16 through access transistors 14. Access transistors 14 are activated by word lines 12. When voltage is applied to word lines 12, a channel below word line 12 conducts, allowing current to flow between diffusion regions 18 and 20 and into or out of storage node 16. Word lines 12 are preferably spaced across the smallest possible distance d to conserve layout area. The smallest possible distance is typically a minimum feature size F achievable by the technology.
Referring now to FIG. 2, a cross-section of the layout of FIG. 1 is shown. Elements of FIG. 2 are labeled as described in FIG. 1. Storage nodes 16 are isolated from a doped well 24 by a dielectric collar 26. Shallow trench isolation 28 is provided over storage nodes 16 to electrically isolate the passing word lines 12 formed above storage nodes 16. Diffusion regions 18 of access transistors 14 are connected to storage node 16 by a node diffusion region 30 to a buried strap 32. Node diffusion 30 and buried strap 32 are typically connected by outdiffusing dopants which mix to create a conductive region (node region 30) therebetween.
Shallow trench isolation 28 is formed on the substrate between the deep trench capacitors 10 to define the active area and isolate the deep trench capacitors 10 and following word lines 12. Word lines 12 are formed subsequently on the substrate. Source/drain areas 18/20 are formed by implantation on active areas beside the word lines 12 with word lines 12 and shallow trench isolation 28 as implant masks.
However, when the deep trech capacitors 10 misalign and shift, the interaction between the overlapped deep trench capacitor 10 and the active area decreases the reliability of the DRAM cell. Therefore, there is a need to detect the overlap of active areas and deep trench capacitors on semiconductor memories, especially for DRAM.
Accordingly, an object of the invention is to provide a test key for detecting the overlap of active areas and deep trench capacitors on dynamic random access memories (DRAM) and a detecting method therefor. The test key can be disposed on scribe lines on a wafer for inline monitoring.
A test key for detecting the overlap of active areas and deep trench capacitors on a memory cell, in accordance with the invention, includes: two parallel lines of active areas disposed on the substrate, two parallel first deep trench capacitors disposed on the substrate along the outer side of the two active areas respectively, a rectangular active word line disposed on the substrate, a first passing word line perpendicular to the two active areas disposed parallely on one side of the rectangular active word line and crossing in a substantially perpendicular fashion the two active areas, a second passing word line perpendicular to the active areas disposed parallely outside the first passing word line and crossing in a substantially perpendicular fashion one end of the two active areas, a third passing word line perpendicular to the active areas disposed parallely on the opposite side of the rectangular active word line and crossing in a substantially perpendicular fashion the opposite end of the two active areas, two second deep trench capacitors disposed on the substrate under where the two first passing word lines overlap the two active areas respectively, a first contact disposed on the first active area between the first and second passing word lines, a second contact disposed on the first active area between the third passing word line and the rectangular active word line, a third contact disposed on the second active area between the first and second passing word lines, and a fourth contact disposed on the second active area between the third passing word line and the rectangular active word line.
Preferably, the first deep trench capacitors are shorter than the first and second active areas. Moreover, the rectangular active word line disposed on the substrate covers the entire two first deep trench capacitors and covers a major part of the two active areas with equal length of the first deep trench capacitors.
A method, in accordance with the invention, is further provided to detect the shift and overlap of active areas and deep trench capacitors on a DRAM cell by means of the above test key. According to a preferred embodiment, a substrate is provided with a scribe line and a memory cell area thereon. A test key as disclosed above is formed on the scribe line and numerous memory cells are formed on the memory cell area. A first threshold voltage is obtained according to the voltage level of the first and second contacts and the first gate. A second threshold voltage is obtained according to the voltage level of the third and fourth contacts and the second gate. The overlap degree between the two active areas and the two first deep trench capacitors on the test key is evaluated based on the difference of the first and second threshold voltages. The overlap degree on the memory cells are estimated based on the overlap degree of the test key.
One feature of the present invention is to detect the misalignment of deep trench capacitors and active areas on a memory cell such that the shift degree can be further evaluated accordingly.
Another feature of the present invention is to form the test key on a scribe line of a wafer enabling inline monitoring of the misalignment between deep trench capacitors and active areas on memory cells.
A detailed description is given in the following embodiments with reference to the accompanying drawings.